Mentor Graphics Applications Engineer Consultant - 6022 in Bangalore, India

Applications Engineer Consultant - 6022


Company: Mentor Graphics

Job Title: Applications Engineer Consultant -6022

Job Location: India – Bangalore

Job Category: Sales

Job Duties:

1. As an important member of the Sales team, help grow customer satisfaction with Mentor’s DFT tools by helping them successfully deploy Automatic Test Pattern Generation (ATPG) and Built In Self-Test (BIST) tools (such as Fastscan, TestKompress, MemoryBIST, LogicBIST, BoundaryScan, SOCScan).

2. Work with customers with varying design styles and methodologies to architect the most effective solution for Design-for-Test.

3. Recognize and communicate potential business opportunities to the account managers to grow Mentor’s business

4. Work collaboratively with customer support engineers, account teams and engineering to successfully deploy Mentor’s products and services

5. Some Travel would be required in this position.

6. Help the account team in growing the business by increasing adoption of

Mentor DFT technology at customers.

7. Deliver training on Mentor’s DFT tools and flows to customers

Job Qualifications:

1. As a member of the technical team, you will contribute to our success by helping customers deploy Mentor’s DFT tools efficiently. This is a challenging position that will assist in growing the DFT business in India. You will work closely with customers as well as customer support and engineering teams.

2. Need excellent communication and problem solving skills, program management skills, hands-on and a self-starter, able to work independently but still build relationships with customers and management.

3. Knowledge and experience with VLSI design, HDL Synthesis, VLSI Testing and Design for Testability.

4. Experience with design, simulation, verification of ASIC/VLSI circuits and systems, design verification and product test generation preferred. In-depth understanding of Design for Test (DFT) structures is required. This includes scan based testing, Compression, Memory BIST, Logic BIST, and Boundary Scan (1149.1). Knowledge of scan data compression methodologies is required.

5. Preferred experience in specific areas: Operating Systems: UNIX, Linux, Sun Solaris.

Languages: Verilog (Behavioral, RTL, gate level), VHDL (Behavioral, RTL, gate level), Perl, C/C++.

CAD Tools: Synthesis, Simulation, ATPG, Compression, Memory BIST, Logic BIST, Boundary Scan. Familiarity with Logic BIST flows and methodologies is a plus.

6. Five to fifteen years of design experience in DFT solution implementation and a good understanding of backend design. Experience in Memory BIST and Logic BIST implementation will be a big plus.

7. Education: Bachelors in Electronics Engineering (min). Masters in Electronics Engineering is a plus