Xilinx, Inc. Design Engineer 2 in India
As part of the fullchip integration team, the candidate would be working on integrating SOC/FPGA products, integrating custom, semi-custom and PNR blocks.
Fullchip chip design, analysis and Methodology development at cutting edge process nodes.
Owning the Design ( schematic/layout ) generation using automated or semi-automated tools, layout supervision and signing off the design for tapeout
Ability to quickly ramp up on new tools and methodologies
DRC, LVS, EM, IR, and DFM at block and chip level
Interface with block owners on IP integration
Automate design flows using scripting ( Perl/Python/Tcl) as necessary
A basic academic understanding of FPGA design architectures would be useful, although not required. As a member of the SoC physical integration team, you'll interface with various engineering groups, including design, CAD, software, and product engineering, across various geographies to work towards the verification and tape out of Xilinx SoC FPGAs.
Master’s/Bachelor’s degree in Electrical/Electronics engineering with 6-9 years experience in custom, semi-custom and/or mixed signal circuit design
Knowledge of and/or experience with industry standard design and verification tools such as Virtuoso, Totem/Redhawk and Calibre.
A good understanding of electrical, timing and reliability issues in deep sub micron circuit design.Should have owned designs and successfully finished 3-4 products.PNR knowledge is desirable but not required.
Ability to plan and work independently and co-ordinate with cross-functional teams across geographies. Strong verbal and non-verbal communication skills.
A good understanding of industry EDA tools used in custom and semi-custom implementation of VLSI designs in cutting edge process nodes.
An automation and scripting mindset is highly desired.
Excellent written and oral communication skills